1. Field of the Invention
The present invention relates to a semiconductor device test circuit for detecting a fault in a semiconductor device, and more particularly, to a semiconductor device test comprising flip-flop circuits each including a racing prevention circuit.
2. Description of the Related Art
Semiconductor device process technology has been improved in recent years, and the scale of the system circuit constituting a semiconductor device (LSI) has been enlarged. In accordance therewith, it has become necessary to incorporate in a system circuit a test circuit (SCAN circuit) for detecting faults in a developed system circuit.
FIG. 4 is a diagram showing a system circuit having a SCAN circuit. In FIG. 4, a SCAN circuit has a structure, in which a plurality of test flip-flop circuits SCAN-FF (In FIG. 4, there are 4 SCAN-FF, that is, SCAN-FF 1, SCAN-FF 2, SCAN-FF 3, and SCAN-FF 4) connected in a chain. That is, the SCAN-out terminal of each SCAN-FF is connected to the SCAN-in terminal of the next SCAN-FF. Further, as is clear from the figure, each SCAN-FF constituting the SCAN circuit is a circuit having a D flip-flop, and is part of system circuit 1. Therefore, in the ordinary operation of system circuit 1, a system signal is inputted at the D terminal of each SCAN-FF, and a system signal is outputted from the Q terminal.
FIG. 5 is an example of the constitution of a SCAN-FF. The SCAN-FF shown in the figure is a circuit called a racing prevention circuit-equipped MUX-D-type SCAN-FF. In FIG. 5, the portion enclosed by a dotted line (portion comprising 2 latch circuits (LATCH1, LATCH2) and an inverter (INVERTER1)) constitutes a D flip-flop. And, a selector is connected to the D terminal of LATCH1. The selector supplies to the D terminal of LATCH1 either a system signal from the system circuit, or a SCAN-DATA signal, which is a test signal, via a SCAN-MODE signal inputted at a SCAN-MODE terminal (SM terminal). For example, when the SCAN-MODE signal is High (xe2x80x981xe2x80x99), the selector selects a system signal from the SCAN-FF D terminal, and when the SCAN-MODE signal is Low (xe2x80x980xe2x80x99), the selector selects a SCAN-DATA signal from the SCAN-FF SCAN-in terminal.
Furthermore, the SCAN-FF shown in the figure has a latch circuit (LATCH3) for preventing racing. Racing refers to a phenomenon, in which circuit operation becomes unstable due to a deviation between the clock timing inputted to each SCAN-FF, and the timing of a SCAN-DATA signal inputted at an Si terminal. A clock signal is supplied from an inverter (INVERTER2) to LATCH3, and Q output of LATCH2 is inputted at the D terminal of LATCH3. The Q terminal of LATCH3 constitutes the SCAN-out terminal for the SCAN-FF.
FIG. 6 is a timing chart of a SCAN-FF. As shown in FIG. 6, the SCAN-FF latches the SCAN-in terminal state at the rising edge of the clock signal, and outputs this latched state from the Q terminal. Furthermore, the latched state is outputted from the SCAN-out terminal at the falling edge of the next clock signal.
A case in which a SCAN-DATA signal for a test is selected in a SCAN circuit, in which SCAN-FF are connected in a chain like this, will be explained hereinbelow.
FIG. 7 is a timing chart of a case in which there is selected a SCAN-DATA signal from the SCAN-in terminal in the SCAN circuit of FIG. 4. In FIG. 7, when test is selected, a SCAN-MODE signal is driven Low, and a SCAN operation (test) commences. At this time, this SCAN operation period is set to clock periods of the number of flip-flops comprising the SCAN circuit. Therefore, when a test is implemented for the SCAN circuit shown in FIG. 4, the SCAN operation period constitutes 4 clock periods (Hereinafter, for the sake of explanation, the 4 clocks in the SCAN operation period are referred to in order as clocks CK1, CK2, CK3, CK4.).
When a SCAN-DATA signal is selected by a SCAN-MODE signal, first, a SCAN-DATA signal (pulse P) is inputted from the SCAN-in terminal (hereinafter referred to as Si terminal) of SCAN-FF1. SCAN-FF1 latches the state of SCAN-DATA signal P (L state in the figure) at the rising edge of clock CK1, and outputs the latched state from the SCAN-out terminal (hereinafter referred to as So terminal)at the falling edge of the next clock CK2. The outputted signal from the So terminal of SCAN-FF1 is inputted at the Si terminal of SCAN-FF2 at practically the same time as it is outputted. And then, SCAN-FF2, similar to SCAN-FF1, latches the state of SCAN-DATA signal P at the rising edge of clock CK2, and outputs the latched state from the So terminal at the falling edge of the next clock CK3.
Similarly, SCAN-FF3 latches the state inputted at the Si terminal thereof at the rising edge of clock CK3, and outputs the latched state from the So terminal at the falling edge of the next clock CK4. Furthermore, SCAN-FF4 latches the state inputted at the Si terminal thereof at the falling edge of clock CK4.
At this time, because the SCAN operation period ends after clock CK4 rises and before the next clock CK5 falls, the SCAN-DATA signal outputted from the So terminal of SCAN-FF4 cannot be acquired during the SCAN operation period. The problem was, by using the latch circuit (LATCH3) for preventing racing in this manner, the SCAN-FF could not detect the SCAN-DATA signal outputted from the So terminal of the final stage SCAN-FF (SCAN-FF4 in FIG. 4) during the SCAN operation period since the signal inputted from the Si terminal generated a delay of approximately 1 clock cycle until outputted from the So terminal.
Consequently, in the past, it was necessary to change the number of clocks of the SCAN operation period at the system circuit design CAD tool (software) side. However, as explained hereinabove, the SCAN operation period is set beforehand in the CAD tool to clock periods of the number of SCAN-FF, and changing the program in the CAD tool is not easy.
Therefore, an object of the present invention is to provide a semiconductor device test circuit that enables the SCAN operation period to be adjusted by simpler means.
To achieve the above-mentioned object, in the present invention, a period adjusting flip-flop is added to the final stage of a SCAN circuit incorporated in a system circuit constituting a semiconductor device (LSI). In accordance therewith, the SCAN operation period can be easily adjusted.
For example, the constitution of the present invention for achieving the above-mentioned object is a semiconductor device test circuit for testing a system circuit constituted on a semiconductor device, said semiconductor device test circuit comprising:
n number of test flip-flop circuits, each including a racing prevention circuit; and
an additional flip-flop circuit,
wherein said test flip-flop circuits constitute a portion of said system circuit, a test signal output terminal of a kth (k is 1 through nxe2x88x921) test flip-flop circuit is connected to a test signal input terminal of the (k+1)th test flip-flop terminal, and the test signal outputted from the nth test flip-flop circuit is inputted to said additional flip-flop circuit.
In a constitution such as this, by outputting a test signal from the Q terminal of the additional flip-flop circuit, it is possible for the test signal to be outputted within the SCAN operation period.